Validation Engineer

Our client, Semiconductor/SoC Validation is seeking a Validation Engineer 3 to join their team. As a Validation Engineer 3, you will be part of the Production Test Engineering team supporting high-volume manufacturability for SoC devices integrating copackaged optics (CPO) SerDes interfaces. The ideal candidate will have hands-on ATE program development experience, strong SerDes/PHY and protocol fundamentals (including UCIe and PCIe production checks), and the ability to translate characterization results into robust multisite production test coverage. You will align successfully in the organization by owning test development end-to-end, collaborating across silicon/firmware/DFT/OSAT teams, and using Python-based automation to improve yield, quality, and throughput.

Job Title:Validation Engineer 3

Location:San Jose, CA

Pay Range:

What's the Job?

• Own development, integration, and maintenance of wafer sort and final test programs on ATE for SoC SerDes with copackaged optics (CPO) interfaces.
• Define and implement production test coverage for SerDes PHY and protocol features, including PRBS, loopback, margining, FEC, CDR lock, and EQ settings, leveraging on-die BIST/DFT and ATE instrumentation.
• Optimize multisite strategies to reduce test time while meeting quality and coverage goals, including parallel execution, guardbanding, and robust pass/fail criteria.
• Correlate bench/characterization results to ATE by building golden-unit flows, establishing limits, and closing gaps between characterization and production performance.
• Integrate DFT features (scan/ATPG, boundary scan, MBIST/LBIST, JTAG) into production flows, managing pattern conversion, timing sets, and pin maps.

What's Needed?

• Hands-on experience developing on leading ATE platforms (e.g., Advantest V93K/AC+ or Teradyne UltraFLEX/UltraFLEXplus), including timing sets, DC/AC measurements, and multisite execution.
• Strong SerDes/PHY fundamentals: equalization, CDR, CTLE/DFE, PRBS/BER, margining, jitter/eye constraints, and on-die BIST integration into production test.
• Proficiency in Python for automation and data analytics, including STDF parsing, visualization, and automated SPC/anomaly detection workflows.
• Solid DFT background: scan/ATPG patterns, boundary scan, MBIST/LBIST, JTAG access, pattern formats (WGL/STIL), and pattern bring-up on ATE.
• Working knowledge of UCIe and PCIe from a production test perspective (e.g., link training emulation, LTSSM state verification via firmware/test hooks, compliance counters, and error injection/monitoring).

What's in it for me?

• Opportunity to lead hands-on production test development for advanced SoC SerDes with copackaged optics.
• Direct impact on yield, quality, and high-volume manufacturability through characterization-to-production test handoff.
• Collaboration with silicon design, firmware, DFT, product engineering, OSAT/probe, and SI teams to qualify ECOs and revisions.
• Use of Python-based tooling to streamline ATE control, STDF analytics, dashboards, and automated limit updates.
• Clear ownership of test plans, specifications, vector maps, limits, release notes, and training support for operations and sustaining engineering.

Upon completion of waiting period consultants are eligible for:

• Medical and Prescription Drug Plans
• Dental Plan
• Vision Plan
• 401(k), Plus Match
• Weekly Pay

If this is a role that interests you and you'd like to learn more, click apply now and a recruiter will be in touch with you to discuss this great opportunity. We look forward to speaking with you!

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