Sr Design Verification Engineer - RISC-V & CPU

Design Verification Engineer - Senior Level (15+ years)
Duration: 10-12+ Months Contract
Locations: Remote (California, oregon, Washington)
Pay Range: $80-$85/hr on W2, 40 Hrs

Description:
The top 6 are must skills and rest are preferred skills, and of course it goes without saying that basic DV skills such as System Verilog/UVM, assertions, coverage, random constraints, etc.

1)           RISC-V architecture knowledge and verification experience
2)           VC Formal DPV App (Datapath Verification) which checks the RTL against C/C++ models for arithmetic conformance
3)           L3 cache coherent system with AXI and CHI interfaces
4)           C/C++
5)           Synopsys tools, VCS, VC Formal
6)           Python based simulation flow
7)           Wide Vector Unit and a Matmul Unit.
8)           Formal verification
9)           SOC System integration is also required, like booting Linux OS
10)         GLS (Gate Level Simulation)
11)         Low Power experience (CPF/UPF)